Referring first to FIG. 1, a circuit 10 is shown for bidirectionally buffering digital signals between, for example, first and second digital signal buses 12, 14. For purposes of explanation, buses 12, 14 will be described as 8 bit data buses.
Circuit 10 includes eight, generally parallel connected, bidirectional bit buffer circuits, indicated at B0-B7. Bit buffer circuits B0-B7 are identical in construction, and only circuit B0 is described and shown in detail herein.
Bit buffer circuit B0 comprises two generally parallel bit buffer paths, the first path comprising a receiver 16, latch 18, and driver 20 connected seriatim. In the second of the bit buffer paths, a receiver 22, latch 24, and driver 26 are also connected seriatim, and in opposite order to the corresponding components of the first path. Receivers 16, 22 comprise conventional logical bit receivers. Drivers 20, 26 comprise conventional logical bit drivers, each including a control terminal 28, 30, respectively, for selectively placing the output in an active or a high-impedance state. Latches 18, 24 comprise conventional transparent latches, each including a control terminal 32, 34, respectively, for selectively placing the latch in a latched or pass-through (i.e. transparent) state.
A parity generator 36 is provided, the inputs of the parity generator being connected to the inputs of receivers 16 in each of circuits B0-B7. Parity generator 36 comprises a conventional parity "tree" of logical exclusive-OR gates. For purposes of explanation, a memory device 38, for example a dynamic random access memory (RAM), is shown connected to data bus 14.
In operation, circuit 10 functions generally to bidirectionally buffer data between buses 12 and 14. In one exemplary application, buses 12, 14 function as local data buses in a computer system (not shown), with bus 12 interfacing a microprocessor and bus 14 interfacing memory 38. In accordance with its buffering function, when data is to be communicated from bus 12 to bus 14, an appropriate signal is applied to control terminal 30 so as to place driver 26 in a high impedance state. Data, in the form of a high or low logical bit 0, is sensed by receiver 16 and converted to another logical level (i.e. 1 or 0). Receiver 16 thus functions in a standard manner to convert widely ranging levels of input signals to narrower ranging levels of output signals. A signal is applied to control terminal 32 for appropriately latching or passing bit 0 through latch 18. The data at the output of latch 18 is then sensed by driver 20, which is controlled via terminal 28 so as to be in the active mode for driving bus 14. Data is transmitted in substantially the identical manner from bus 14 to bus 12 via the path including receiver 22, latch 24, and driver 26.
Parity generator 36 provides the capability to generate a parity bit responsive to the data on bus 12. When such parity generation is desired, the data on bus 12 is frozen for a time sufficient to permit parity generator 36 to operate on the data and generate the parity bit. Parity generator 36 further provides the capability to generate a parity bit responsive to the data on bus 14, with the data either being latched in or passed through latch 24.
When applied in a computer environment of the type described above, circuit 10 exhibits the substantial disadvantage of interrupting data transmission on bus 12 whenever it is desired to generate a parity bit. More specifically, when parity is generated responsive to data on bus 12, the data must be frozen on bus 12 for a time sufficient to allow parity generator 36 to function. Similarly, when it is desired to generate a parity bit responsive to the data on bus 14, the data must be frozen on bus 14 or latched in latch 24. In either of these conditions, the data is present at the output of driver 26, and thus it is necessary to interrupt data transmission on bus 12.